Dynamic logic circuits of the domino type, according to the prior art, use pre-charging circuits on an evaluation node to reset the circuit's output. Referring to FIG. 1, dynamic logic circuit 100 in accordance with the prior art is shown. Dynamic logic circuit 100 includes N-tree logic 101 which performs a logical calculation in response to input signals 102-106. The logical calculation is implemented by an N-tree stack, including NFET devices 107-111 in dynamic logic circuit 100. Each of input signals 102-106 is coupled to a corresponding gate of NFET devices 107-111.
The logical calculation is performed during an evaluate phase of clock 112. In its evaluate phase, clock 112 turns off p-type field effect transistor (PFET) device 113 and turns on a foot transistor, n-type field effect transistor (NFET) device 114. The output of N-tree logic 101 appears on evaluation node "N". The signal on evaluation node "N" is inverted at an output 115 of dynamic logic circuit 100 by PFET device 116 and NFET device 117. PFET device 118 forms a half latch that maintains the logic state on evaluation node "N" when it is precharged to a "high" logic level.
Prior to evaluation, evaluation node "N" is pre-charged during a pre-charge phase of clock 112. The pre-charge phase of clock 112 turns on PFET device 113 coupling evaluation node "N" to a voltage supply. Substantially simultaneously, NFET device 114 is turned off, decoupling a "foot" node of N-tree logic 101 from ground. The coupling of node "N" to the voltage supply resets output 115 by turning on NFET device 117 thereby discharging output 115 by coupling output 115 to ground.
Thus, in dynamic logic circuit 100 in accordance with the prior art, the reset of output 115 is through the evaluation path. In other words, the dynamic logic circuit 100 reset and evaluation paths are coupled, and an increase in the evaluation path load on the evaluation node adversely affects the reset timing. Conversely, any increase in the reset path sizing detrimentally affects the evaluation path timing.
Thus, there is a need in the art for a reset mechanism that decouples the reset of the dynamic logic circuit from the evaluation path, and which permits improved circuit performance for a wide range of sizing, output loading, and noise requirements. Although dynamic logic 100 has been illustrated to be of the footed type, dynamic logic circuits of the delayed reset, and pseudo-clocked types, in accordance with the prior art, behave in substantially the same way during pre-charge and evaluate phases. Therefore, there is a need for a decoupled reset mechanism in dynamic logic circuits of these types as well.